The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a nanosheet field-effect transistor and methods of forming a structure for a nanosheet field-effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate electrode configured to switch carrier flow in a channel formed in the body region. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in an inversion or depletion layer in the channel between the source and drain to produce a device output current. The body region and channel of a planar field-effect transistor are located beneath the top surface of a substrate on which the gate electrode is supported.
A fin-type field-effect transistor (FinFET) is a non-planar device structure for a field-effect transistor that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET includes a fin that defines a body region of semiconductor material, heavily-doped source/drain regions formed in sections of the body, and a gate electrode that wraps around a channel located in the fin body during operation between the source/drain regions. In comparison with planar field-effect transistors, the arrangement between the gate structure and fin body improves control over the channel and reduces the leakage current when the FinFET is in its ‘Off’ state. This, in turn, enables the use of lower threshold voltages than in planar field-effect transistors, and results in improved performance and lowered power consumption.
Nanosheet field-effect transistors have been developed as an advanced type of FinFET that may permit additional increases in packing density in an integrated circuit. The body of a nanosheet field-effect transistor includes multiple nanosheet channel layers vertically stacked in a three-dimensional array. Sections of a gate stack may surround all sides of the individual nanosheet channel layers in a gate-all-around arrangement. The nanosheet channel layers are initially arranged in a layer stack with sacrificial layers composed of a material (e.g., silicon-germanium) that can be etched selectively to the material (e.g., silicon) constituting the nanosheet channel layers. The sacrificial layers are etched and removed in order to release the nanosheet channel layers, and to provide spaces for the formation of the gate stack.